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W948D6FB / W948D2FB
256Mb Mobile LPDDR
6.6.1 Extended Mode Register Definition
BA1
BA0
An....A8 (1)
A7 ~ A5
A4
A3
A2
A1
A0
Address Bus
1
0
0 ( 2)
DS
Reserved
PASR
Extended Mode Reg.
A7
0
0
0
0
1
A6
0
0
1
1
0
A5
0
1
0
1
0
Drive Strength
Full Strength Driver
Half Strength Drive
Quarter Strength Driver
Octant Strength Driver
Three-Quarters Strength Driver
A2
0
0
0
0
A1
0
0
1
1
A0
0
1
0
1
PASR
All banks
1/2 array (BA1=0)
1/4 array (BA1=BA0=0)
Reserved
1
1
1
0
0
1
0
1
0
Reserved
Reserved
Reserved
NOTES:
1
1
1
Reserved
1.MSB depends on mobile DDR SDRAM density.
2.A logic 0 should be programmed to all unused / undefined bits to ensure future compatibility.
6.7 Status Register Read
Status Register Read (SRR) is an optional feature in JEDEC, and it is implemented in this device. With SRR, a
method is defined to read registers from the device. The encoding for an SRR command is the same as a MRS with
BA[1:0]=”01”. The address pins (A[n:0]) encode which register is to be read. Currently only one register is defined at
A[n:0]=0. The sequence to perform an SRR command is as follows:
?
?
?
?
?
?
?
All reads/writes must be completed
All banks must be closed
MRS with BA=01 is issued (SRR)
Wait tSRR
Read issued to any bank/page
CAS latency cycles later the device returns the registers data as it would a normal read
The next command to the device can be issued tSRC after the Read command was issued.
The burst length for the SRR read is always fixed to length 2.
Publication Release Date : Oct, 15, 2012
- 16 -
Revision : A01-004
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